In many large commercial data processors, such as the IBM System/370 Model 168, the bus width for each transfer of data between the processor storage control function (PSCF) and the instruction unit function (IPPF) is a double word (DW). When larger amounts of data are to be transferred, multiple DW cycles are taken. However, if a cache (i.e. buffer storage) is provided in the PSCF, it is common for the line size (smallest amount of data which can be loaded into the cache from main storage) to be several (2, 4, 8 or 16) double words. The line size is selected to optimize the performance of the system. A smaller size could cause performance loss because more lines would need to be transferred, and a larger size could cause performance loss because line transfers would take longer. Because of the mismatch between bus size and line size, it requires multiple cycles to load a line in a cache; and during those cycles, the line being transferred to the cache is unavailable to satisfy processor requests for data.